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| VSC8115YA资料 | |
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VSC8115YA PDF Download |
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File Size : 116 KB
Manufacturer:VITESSE Description:During normal data transfer, the SDATA signal only changes when the SCLK signal is low, and is stable when SCLK is high. There are two exceptions to this. A high to low transition on SDATA while SCLK is high is used to indicate the start of a data transfer cycle. A low to high transition on SDATA while SCLK is high indicates the end of a data transfer cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer cycle is a 7-bit address with a Read/Write bit (R/W#) as the LSB. R/W# = 1 in read mode. R/W# = 0 in write mode. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：VSC8115YA 厂 家：VITESSE 封 装：TSSOP20 批 号：01 数 量：35 说 明：绝对原装正品底价 |
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运 费： 所在地： 新旧程度： |
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| 联系人：龙先生,胡小姐 |
| 电 话：0755-83226907,83229025,83226903 |
| 手 机：13927436669 |
| QQ：1109170345,514620629 |
| MSN：hlh1999@msn.com |
| 传 真：0755-83226930 |
| EMail：sale@cdf-ic.com |
| 公司地址： 深圳市福田区中航路新亚洲电子商城国利大厦710室. |
