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| TSOT042G5-3BLL15资料 | |
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TSOT042G5-3BLL15 PDF Download |
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File Size : 116 KB
Manufacturer:AGERE Description:Moreover, data of Q00 to Q07 are written into 2-line delay data only memory in synchronization with rise edge of RCK. At this time, the write address of 2-line delay data only memory is incremented. The read functions given below are also performed in syn- chronization with rise edge of RCK. When RE is H, a read operation from both of 1-line delay data only memory and 2-line delay data only memory is inhib- ited and the read address counter of each memory is stopped. The outputs of Q00 to Q07 and Q10 to Q17 are in the high impedance state. Moreover, a write operation to 2-line delay data only memory is inhibited and the write address counter of 2-line delay data only memory is stopped. When read reset input RRES is L, the read address counter of 1-line delay data only memory, and the write address counter and read address counter of 2-line delay data only memory are initialized. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：TSOT042G5-3BLL15 厂 家：AGERE 封 装：BGA 批 号：01 数 量：10 说 明：绝对原装正品底价 |
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运 费： 所在地： 新旧程度： |
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