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| SN75LVDS82DGG资料 | |
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SN75LVDS82DGG PDF Download |
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File Size : 116 KB
Manufacturer:TI Description:¶ Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：SN75LVDS82DGG 厂 家：TI 封 装：TSSOP56 批 号：07+ 数 量：6400 说 明：绝对原装深圳现货/底价 |
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