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| SN105124DGSR资料 | |
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SN105124DGSR PDF Download |
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File Size : 116 KB
Manufacturer:TI Description:A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：SN105124DGSR 厂 家：TI 封 装：SOP 批 号：06+ 数 量：14000 说 明：绝对原装深圳现货/底价 |
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