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| SI4205-BMR资料 | |
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SI4205-BMR PDF Download |
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File Size : 116 KB
Manufacturer:SILICON CHI Description:Burst Read Accesses The CY7C1350G has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. |
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型 号：SI4205-BMR 厂 家：SILICON CHI 封 装：LGA28 批 号：06+ 数 量：44,076 说 明：绝对原装深圳现货/底价 |
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