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| PCF5001H-2资料 | |
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PCF5001H-2 PDF Download |
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File Size : 116 KB
Manufacturer:PHILIPS Description:SERIAL DATA INTERFACE TIMING When a 16Mb/s serial data rate is required, the master clock frequency will be running at 16.384MHz resulting in a single-bit per clock. For all other cases, 2Mb/s, 4Mb/s, and 8Mb/s, the master clock frequency will be twice the fastest data rate on the serial streams. Use Table 5 to determine clock speed and DR3-0 bits in the Control Register to setup the device. The PCF5001H-2 provides two different interface timing modes, ST-BUS® or GCI. The PCF5001H-2 automatically detects the presence of an input frame pulse and identifies it as either ST-BUS® or GCI. In ST-BUS®, when running at 16.384MHz, data is clocked out on the falling edge and is clocked in on the subsquent rising-edge. At all other data rates, there are two clock cycles per bit and every second falling edge of the master clock marks a bit boundary and the data is clocked in on the rising edge of CLK, three quarters of the way into the bit cell. See Figure 15 for timing. In GCI format, when running at 16.384MHz, data is clocked out on the rising edge and is clocked in on the subsquent falling edge. At all other data rates, there are two clock cycles per bit and every second rising edge of the master clock marks the bit boundary and data is clocked in on the falling edge of CLK at three quarters of the way into the bit cell. See Figure 16 for timing. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：PCF5001H-2 厂 家：PHILIPS 封 装：QFP 批 号：0223/0225+ 数 量：1323 说 明：绝对原装深圳现货/底价 |
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运 费： 所在地： 新旧程度： |
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| 联系人：龙先生,胡小姐 |
| 电 话：0755-83226907,83229025,83226903 |
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| 传 真：0755-83226930 |
| EMail：sale@cdf-ic.com |
| 公司地址： 深圳市福田区中航路新亚洲电子商城国利大厦710室. |
