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| MMBT3904资料 | |
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MMBT3904 PDF Download |
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File Size : 116 KB
Manufacturer:ON/长电 Description:pins together. When the PE input is LOW, the LS195A appears as four common clocked D flip-flops. The data on the parallel inputs P0, P1, P2, P3 is transferred to the respective Q0, Q1, Q2, Q 3 outputs following the LOW to HIGH clock transition. Shift left operations (Q3 Q2) can be achieved by tying the Qn Outputs to the PnC1 inputs and holding the PE input LOW. All serial and parallel data transfers are synchronous, occurring after each LOW to HIGH clock transition. Since the LS195A utilizes edge-triggering, there is no restriction on the activity of the J, K, Pn and PE inputs for logic operation except for the set-up and release time requirements. A LOW on the asynchronous Master Reset (MR) input sets all Q outputs LOW, independent of any other input condition. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：MMBT3904 厂 家：ON/长电 封 装：SOT23 批 号：07+ 数 量：122055 说 明：订货5-7天 |
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运 费： 所在地： 新旧程度： |
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| 联系人：龙先生,胡小姐 |
| 电 话：0755-83226907,83229025,83226903 |
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| 公司地址： 深圳市福田区中航路新亚洲电子商城国利大厦710室. |
