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| ET-TVT031A-Q资料 | |
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ET-TVT031A-Q PDF Download |
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File Size : 116 KB
Manufacturer:EI Description:When interpolating, the user should normally bring SYNC HIGH for at least one clock cycle, returning it LOW with the first desired input data value. The chip will then continue to accept data on alternate rising edges of CLK. The user may leave SYNC LOW or change its value once per clock cycle, with equivalent results. The chip can be powered up and operated with SYNC grounded, but the input-to-output latency may vary by 1/2 input sample period and the host system wont know which (even- or odd-numbered) CLK rising edges strobe the input register. The setup and hold tim- ing requirements for SYNC, with respect to the rising edges of CLK, are the same as those for all other data and control inputs except OE, which is asynchronous. In two-channel mode, it must remain low after the first incoming data value. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：ET-TVT031A-Q 厂 家：EI 封 装：QFP52 批 号：0238+ 数 量：357 说 明：绝对原装深圳现货/底价 |
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