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| CD54HCT27F资料 | |
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CD54HCT27F PDF Download |
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File Size : 116 KB
Manufacturer:HARRIS Description:Eighteen address bits are required to decode 1 of 262 144 storage cell locations. Nine row-address bits are set up on A0 through A8 and latched onto the chip by RAS. Then, nine column-address bits are set up on A0 through A8 and latched onto the chip by the first xCAS. All addresses must be stable on or before the falling edge of RAS and xCAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. xCAS is used as a chip select, activating its corresponding output buffer and latching the address bits into the column-address buffers. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：CD54HCT27F 厂 家：HARRIS 封 装：DIP14 批 号：9536+ 数 量：96 说 明：绝对现货特价 |
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运 费： 所在地： 新旧程度： |
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