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| 8B332资料 | |
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8B332 PDF Download |
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File Size : 116 KB
Manufacturer: Description:Target Ready: As a target, this signal will be asserted low when the (slave) device is ready to complete the current data phase transaction. This signal is used in conjunction with the IRDYN signal. Data transaction takes place at the rising edge of PCICLK when both IRDYN and TRDYN are asserted low. As a master, this signal indicates that the target is ready for the data during write operation and with the data during read operation. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：8B332 厂 家： 封 装：SOP 批 号： 数 量：1,938 说 明：绝对原装深圳现货/底价 |
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