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| 74HC4052PW118资料 | |
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74HC4052PW118 PDF Download |
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File Size : 116 KB
Manufacturer:PHILIPS Description:Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling edge of RAS. The buffers act as transparent or flow-through latches while xCAS is high. The first falling edge of xCAS latches the column addresses. This feature allows the devices to operate at a higher data bandwidth than conventional page-mode parts because data retrieval begins as soon as column address is valid rather than when xCAS transitions low. This performance improvement is referred to as enhanced page mode. A valid column address can be presented immediately after tRAH ( row-address hold time ) has been satisfied, usually well in advance of the falling edge of xCAS. In this case, data is obtained after tCAC max ( access time from xCAS low) if tAA max ( access time from column address) has been satisfied. In the event that column addresses for the next page cycle are valid at the time xCAS goes high, minimum access time for the next cycle is determined by tCPA ( access time from rising edge of the last xCAS). |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：74HC4052PW118 厂 家：PHILIPS 封 装：TSOP 批 号：2006年12月 数 量：1874 说 明：绝对原装正品底价 |
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