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| 70232-921资料 | |
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70232-921 PDF Download |
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File Size : 116 KB
Manufacturer: Description:Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the address during the clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition. The outputs are automati- cally tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：70232-921 厂 家： 封 装：信号头(4Χ6) 批 号：01+ 数 量：549 说 明：绝对原装正品底价 |
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